The manufacturing side of the CHIPS Act gets all the headlines. Fab groundbreakings, ribbon cuttings, TSMC Arizona updates. But a GAO report released this week reveals that the other half of the law — the $11 billion earmarked for advanced semiconductor R&D — has been quietly dismantled, with no credible plan to rebuild it.
That's a problem worth sitting with. You can pour concrete faster than you can develop a process node. If the U.S. doesn't have functioning R&D infrastructure, the fabs it's building will eventually run out of road.
$7.8 Billion Canceled, No Replacement Timeline
The numbers from the GAO's new report are stark. Commerce canceled awards representing $7.8 billion of the $11 billion appropriated for advanced microelectronics R&D activities. The three pillars of that program — the National Semiconductor Technology Center (NSTC), the National Advanced Packaging Manufacturing Program (NAPMP), and the Industrial Advisory Committee — are all either canceled, paused, or lapsed.
The NSTC's award was canceled in 2025. Commerce says it plans to reestablish the center, but the plan is not sufficiently detailed to show how it will meet relevant statutory requirements, according to GAO. The NAPMP awards were paused or terminated. The Industrial Advisory Committee's charter was simply not renewed.
The agency's explanation is that these programs don't align with current administration priorities. That's a coherent political choice. What's not coherent is having no documented timeline for meeting the statutory requirements that Congress wrote into law when it passed the CHIPS and Science Act. GAO's recommendation is blunt: develop a detailed plan. Commerce, as of the report's publication, had not done so.
The manufacturing incentives program, by contrast, is actually moving. As of July 15, 2026, Commerce had funded 49 projects across 24 companies, up from 40 projects a year ago. Disbursements stand at $13.1 billion — roughly 42 percent of the $31.5 billion in direct funding. Awardees have met all required milestones by their due dates, though some fell behind anticipated schedules. That's a reasonable execution record for a program of this complexity.
But 42 percent disbursed with the R&D infrastructure gutted is a telling ratio. The U.S. is building factories faster than it's building the research base those factories will eventually depend on.
The Equity-for-Funding Experiment
Separately, Commerce has been experimenting with a new funding mechanism: taking minority equity stakes in semiconductor companies in exchange for R&D grants. The department announced over $870 million in incentives distributed across seven companies, including up to $300 million for GlobalFoundries and up to $245 million for Kepler, focused on AI memory and logic.
This follows the more controversial precedent of a reported 10% stake in Intel tied to $11 billion in subsidies — a structure that Commerce Secretary Howard Lutnick framed as boosting domestic semiconductor capabilities and creating high-paying jobs. The equity model is presented as protecting taxpayer interests: if the companies succeed, the government participates in the upside. The skeptical read is that it's also a way to deploy capital without the accountability structures that came with the canceled NSTC and NAPMP programs, which were supposed to provide independent technical oversight and industry coordination.
An equity stake in a private company is not a substitute for a functioning national semiconductor technology center. One is a financial instrument; the other is supposed to be infrastructure for the entire industry. GAO flagged that without a detailed plan for reestablishing these entities in line with statute, Commerce may miss opportunities to advance U.S. semiconductor technologies — leaving the country reliant on other nations for critical capabilities.
The Polysilicon Tariff Adds Another Variable
This week also brought a new trade action that touches the chip supply chain at its most upstream point. The White House imposed a 15% tariff and a series of price floors on products made from polysilicon — the ultra-pure silicon that sits at the start of both semiconductor and solar manufacturing supply chains. Implementation is delayed until December 4.
The stated goal is protecting domestic polysilicon production from Chinese competition. China dominates global polysilicon supply, and the administration's concern that this creates a chip supply chain vulnerability is legitimate. Reuters first reported the administration's plan to pursue a hybrid system combining minimum import prices with tariffs — a structure that landed in the final proclamation largely as described.
The question, as always with upstream tariffs, is who absorbs the cost in the interim. U.S. semiconductor manufacturers that currently source polysilicon from international suppliers will face higher input costs starting in December, at least until domestic production scales — which takes years, not months. The tariff announcement landed the same week the GAO confirmed the R&D programs designed to accelerate domestic materials and process development have been canceled. The sequencing is uncomfortable: restrict foreign supply inputs while simultaneously dismantling the research programs that would help domestic producers close the gap.
What to Watch
The GAO report gives Commerce a specific accountability target: produce a detailed plan and timeline for reestablishing the NSTC, NAPMP, and Industrial Advisory Committee in line with statutory requirements. Watch for whether Commerce responds with a documented plan or continues operating without one — that response, or its absence, will tell you more about the administration's actual semiconductor strategy than any ribbon-cutting ceremony.
The December 4 polysilicon tariff implementation date is the next hard deadline. Between now and then, watch for domestic manufacturers to disclose input cost impacts in Q3 earnings calls. That's where the real price of this policy will first become visible.
